The present invention relates to a fault simulation method and apparatus which make a list of faults in a semiconductor integrated circuit that are detectable using a certain test pattern sequence.
In a conventional fault simulation of a semiconductor integrated circuit (hereinafter referred to as a semiconductor IC or simply as an IC), predetermined test patterns are input to the semiconductor IC with faults assumed to lie therein, then response output values available from its output terminal are calculated by a logic simulation to detect variations in the output values relative to those obtainable under fault-free conditions, and the results thus obtained are summarized as a comparative table of assumed faults and input/output logic values, which table is commonly called a fault dictionary. This is a conventional way of making a list of faults detectable by the test patterns. In the testing of an IC each test pattern is input thereto, and its response output value and the input value are used to refer to the fault dictionary to decide whether the IC is under faulty conditions and, if any, locate which part or parts of the IC are faulty.
Further, to cope with faults that do not cause logic faults, such as a bridging fault and a current leak fault, there has been proposed a fault simulation method that uses, in combination, an IDDQ (quiescent power supply current) testing scheme and a logic simulation. According to this method, the logic simulation is used to calculate logic signal values that develop on signal lines in the IC in response to a certain test pattern applied thereto, and a list of detectable fault is made by enumerating faults which satisfy the criteria for the occurrence of IDDQ abnormalities with the faults assumed to lie in the IC. Upon application of a certain test pattern to an IC, each signal line usually has a logic value “0” or “1.” On this account, when a bridging fault occurs between the signal lines having the logic values “0” and “1,” respectively, the IC develops an IDDQ abnormality. Accordingly, bridging faults between all signal lines of the logic values “0” and “1” in the IC are detectable based on input test patterns by the IDDQ testing scheme, and these bridging faults can be complied into a list of faults detectable by the IDDQ testing scheme.
According to the fault simulation method using the logic simulation, however, the fault model that can be simulated is limited only to a single stuck-at-fault (Stuck-At-0 or Stuck-At-1) which is a fault that one signal line is stuck at a certain state (“0”or “1”). Therefore, it is impossible with this fault simulation method to simulate, with high sensitivity, a multiple stuck-at-fault that plural signal lines are stuck at “0” or “1”, a delay fault, a short fault between lines, and so on; hence, no lists of detectable faults can be made.
Further, the fault simulation method by the combined use of the IDDQ testing scheme and the logic simulation is a method of measuring the power supply current of the semiconductor IC under stable conditions, and is intended primarily for short faults in the circuit. Hence, this method is incapable of making lists of detectable faults on transient phenomena of semiconductor ICs such as delay fault and open faults affecting the delay time and abnormalities of local or global process parameters (a sheet resistance, an oxide film thickness, and so forth).
Accordingly, there is a need for the implementation of a fault simulation method with which it is possible to make a list of faults detectable using a certain test pattern sequence for the above-mentioned delay faults, open faults and parameter abnormality faults.
An object of the present invention is to provide a fault simulation method and apparatus with which it is possible to make a list of faults detectable by a certain test pattern sequence for delay, open and parameter abnormality faults in semiconductor ICs by the combined use of a transient power supply current, IDDQ testing scheme capable of transient phenomenon of the ICs and high in observability and the logic simulation.